The present disclosure relates to a semiconductor memory device and, more particularly, to a column address control circuit in a semiconductor memory device.
Generally, a semiconductor memory such as a SDRAM (Synchronous Dynamic Random Access Memory), which supports a DDR (Double Data Rate) or SDR (Single Data Rate) mode, has a cell structure of even and odd blocks in order to be suitable for a DDR characteristic in which data reading/writing operations are performed at an rising edge of a clock and/or a falling edge of the clock. Typically, the number of even blocks is the same as that of odd blocks.
Address lines are connected to each of the even and odd blocks, and an address counter is connected to each address line.
An even address and an odd address are respectively input to the even and odd blocks through the address counter so that a column is selected in response to a read command for reading out data or a write command for writing data. The even and odd addresses are decoded by column decoders of the even and odd blocks to select a column.
At this time, a length of data processed in the selected column in the read or write operation of the semiconductor memory, is generally called a burst length (BL).
For example, in a case that the BL is 4, when a start address to designate a requested column, in which the data read or write operation starts, is provided from the outside, three additional column addresses are further provided from the internal circuit itself so that the read or write operation is possible on the four data.
That is, for the sequential burst mode having the burst length of 4 and a requested column address of 5, the data words (width of the SDRAM) are accessed in the order of 5, 6, 7 and 4.
Meanwhile, in the conventional SDR SDRAM, the read and write operations are performed on a basis of a burst mode. In a case that a specific address is applied in a high level when a MRS (Mode Register Set) command is applied, the read operation is performed in the burst mode, but the write operation is performed based on one bit data. This is called a BRSW (burst read single write) mode.
However, in the DDR SDRAM, a basic operation is performed based on the burst length of 2 by processing the write operation at the rising and falling edges of a clock. The burst read single write mode, which is supported in the SDR SDRAM, is not prescribed in the specification of the DDR SDRAM.